In the process of fabricating semiconductor devices such as LSI devices, conventionally, a lamination of various kinds of thin layers including metallic layers and insulative layers are formed on a silicon wafer, for example, through various processing steps. As one major for polishing or planarizing an outer or upper most surface of the wafer to obtain a substrate surface having a high degree of planarity, chemical mechanical polishing (hereinafter referred to as “CMP”) is known, wherein a thin disk-shaped polishing pad of synthetic resin material or expanded material thereof may be employed, and the polishing pad and the wafer (semiconductor substrate) are made to undergo relative rotation while supplying between the wafer and the pad a slurry consisting of fine abrasive particles and a suitable kind of liquid, for effect polishing.
In order to meet a great demand for a highly integrated, high-precision semiconductor device, it is required to produce multiple layers of intricate patterns of extremely fine lines. To meet this end, the CMP process is required to ensure (a) “polishing precision”, i.e. the ability to polish an entire wafer surface with highly precise planarization, and (b) “polishing efficiency”, i.e. the ability to polish a wafer with high process efficiency. Higher circuit densities seen in semiconductor devices in recent years have raised the bar still further as regards these two capabilities.
To meet such requirements, there has been proposed polishing pads for use in CMP processes, in which the surface of the polishing pad (i.e. the surface which polishes the wafer) is provided with a multitude of tiny holes, or with linearly extending grooves or radially extending grooves. Pads of this kind are disclosed in Patent Document Nos. 1, 2, 3, for example.
However, notwithstanding the use of these polishing pads of conventional design, it is still exceedingly difficult to achieve both “polishing precision” and “polishing efficiency” at levels adequate to meet requirements. In the field of super LSI in particular, metallic interconnect or metallization width of lines formed on the wafer (line patterns with metal line) is extremely narrow, i.e., 0.18 μm or smaller, and accordingly the surface must be polished to a very low degree of surface roughness (Rz), i.e. 0.25 μm or smaller. Also, the use of recently soft metal such as cooper and gold for metallization has entered the stage of research directed to practical application. In view of the above, still further improvements are required to polishing pads in order to achieve satisfactory levels of polishing precision and polishing efficiency.
As one measures for improving polishing precision in CMP processes, Patent Document No. 4 teaches a polishing pad having grooves that, viewed in cross section, expand in dimension toward the pad surface. According to Patent Document No. 4, the slant side wall of the groove guides the slurry and polishing residues, thus improving polishing precision.
However, research conducted by the inventors has revealed that when grooves like those taught in Patent Document No. 4 are formed on a polishing pad surface, polishing performance, which includes both polishing efficiency and polishing precision is inconsistent. Therefore, practical use would be extremely difficult. It is thought that the major reason for this drawback is the variation in the width dimension of the groove in its depthwise direction.
In addition to wear produced in wafer polishing, a polishing pad is typically subjected to a conditioning process (dressing) by means of abrading the pad surface at predetermined process time intervals. However, the grooves taught in Patent Document No. 4 unavoidably experience appreciable change in groove width due to polishing-induced wear and surface conditioning, and this is accompanied by significant variation in parameters such as the distribution of stress. Thus, consistent polishing characteristics may be not achieved.
(Patent Document No. 1)
    U.S. Pat. No. 5,921,855(Patent Document No. 2)    U.S. Pat. No. 5,984,769(Patent Document No. 3)    U.S. Pat. No. 6,364,749(Patent Document No. 4)    U.S. Pat. No. 6,238,271